1. Field of the Invention
The present invention relates to a method of manufacturing a silicon on insulator (hereinafter, referred to as SOI) which is essential for implementing a semiconductor integrated circuit having ultra large scale integration, very high speed, and low power consumption characteristics, and in particular, to a method of manufacturing an ultra thin body SOI substrate having a uniform thickness and a good interface characteristic of high quality which are essential in manufacture of an nano-class semiconductor device.
2. Discussion of Related Art
In general, an SOI substrate has been developed as a substrate of a next-generation electronic device which is capable of overcoming problems such as unstable insulation between devices and occurrence of parasitic capacitance of the conventional silicon substrate when a large mount of electronic devices are integrated.
A structure of the SOI substrate means a structure that an insulating layer is formed on a silicon wafer and a single crystalline silicon layer is present thereon, and, in a broad sense, means a structure that a silicon single crystal is formed on the top of the insulator regardless of kinds of a lower substrate and an insulating layer.
A technique of manufacturing such an SOI substrate has been progressed with a research of silicon on sapphire (SOS), and a zone-melting and recrystallization (ZMR) method, a porous silicon oxidation method, a lateral epitaxial growth method of silicon, and so forth have been researched in its initial development, however, a separation by implantation of oxygen (SIMOX) technique, a unibond technique using a smart cut, an epitaxial layer transfer (ELTRAN) technique or the like have been a main stream in recent years.
According to the conventional SIMOX technique, oxygen of about 1×1017 to 9×1017 atoms/cm2 is injected into the silicon, which is then subjected to annealing and oxidation at a high temperature of about 1300° C. to 1500° C. for recrystallization of the silicon and stability of the buried oxidation layer and defect removal.
However, according to the conventional SIMOX technique, it is difficult to form a silicon layer having a uniform thickness and a low concentration of impurity, and high defect density at an interface and a region near the interface, and a poor surface roughness can adversely affect a device.
In addition, according to the conventional UNIBOND technique, a smart cut method is employed by which hydrogen ions are first injected into a silicon wafer in which an insulating layer is already formed, which is then bonded with another silicon wafer to have a lower part of the hydrogen ion injection location of the silicon wafer fall off through a subsequent annealing process to thereby form a thin silicon layer, so that effects such as higher crystal quality, higher BOX quality, less surface roughness and low price process in thick film SOI can be expected compared to other methods of the related art, however, a thickness uniformity is still required, and productivity is degraded due to several processes such as a chemical mechanical polishing (CMP) process.
In addition, the conventional ELTRAN technique is one that first forms a porous silicon layer on a silicon wafer and forms a single crystalline silicon layer thereon by an epitaxial growth method, which is then bonded with the silicon wafer where an insulating layer is formed, and subsequently, the silicon bulk and the porous layer are removed by polishing and etching processes to thereby obtain a planarized silicon layer on the insulator, which is relatively advantageous in control of a thickness of the silicon layer, however, it is not good for matching with a conventional complementary metal oxide semiconductor (CMOS) process, and is limited to some applications due to the degradation of film quality, particle occurrence, poor surface roughness, degraded reliability or the like.
As described above, the techniques (SIMOX, UNIBOND, and ELTRAN or the like) for manufacturing an ultra thin body (UTB) SOI substrate used in the manufacture of the UTB SOI CMOS device, do not completely meet requirements of the UTB SOI wafer which requires control on a uniform thickness, low defect density, and an upper silicon thickness of several nanometers in a nano-class device.